1. Field of The Invention
The present invention relates to CMOS memory cells having PMOS and NMOS transistors with a common floating gate. More particularly, the present invention relates to a configuration allowing programming and erasing through the gate oxide of NMOS and PMOS transistors of a CMOS memory cell.
2. Description of the Related Art
FIG. 1 illustrates the configuration of a conventional CMOS memory cell 100 having a PMOS transistor 102 and an NMOS transistor 104 with a common floating gate. Drains of transistors 102 and 104 are connected together to form the output of the CMOS cell 100. Capacitors 106 and 108 are connected to couple voltage to the common floating gate. Bias voltage is provided to the source of PMOS transistor 102 from a chip Vcc pin. Bias voltage is provided to the source of the NMOS transistor 104 through a chip ground or Vss pin. Capacitor 106 supplies voltage from an array control gate (ACG) node. An NMOS pass transistor 110 supplies a word control (WC) voltage to capacitor 108 as controlled by a word line (WL) voltage supplied to its gate. The CMOS memory cell 100 is disclosed in U.S. Pat. No. 5,272,368 entitled "Complementary Low Power Non-Volatile Reconfigurable EECELL," and in U.S. Pat. No. 4,885,719 entitled "Improved Logic Cell Array Using CMOS E.sup.2 PROM Cells."
Typical voltages applied for program, erase and read of the CMOS memory cell 100 are listed in Table I below. Programming indicates electrons are removed from the common floating gate, while erase indicates that electrons are added to the common floating gate.
TABLE I ______________________________________ WC WL ACG Vcc Vss ______________________________________ Program 12 13.8 0 0 0 Erase 0 5 13.8 12 12 Read 2.5 5 2.5 5 0 ______________________________________
FIG. 2A shows a layout for the CMOS cell 100 of FIG. 1, while FIGS. 2B-2E show respective cross sectional views at BB', CC', DD' and EE' in FIG. 2A. The layout for the CMOS cell shown in FIGS. 2A-2E is formed in a p type substrate.
As shown in FIGS. 2A and 2B, capacitor 106 includes n+ type implant regions 202 and 203 formed in the p type substrate. Overlying the n+ type implant regions 202 and 203 is a gate oxide layer (GOX) 204 approximately 150 .ANG. thick. Provided above the gate oxide layer 204 is the common floating gate (F.G.) 206. With a p type substrate beneath the gate oxide 204, during application of a program voltage, with a higher voltage on the substrate than on the common floating gate, the p type region beneath the gate oxide can become depleted forming a p- type region, and preventing tunneling from the common floating gate. To prevent such depletion, additional n.sup.+ dopant is added to the substrate directly beneath gate oxide 204 to form a programming junction (PRJ) region 208 which will not be depleted during programming.
As shown in FIGS. 2A and 2C, capacitor 108 includes n+ implant regions 208 and 209 formed in the p type substrate. Overlying the n+ type implant regions 208 and 209 is a gate oxide 210 which includes a 150 .ANG. portion 211 and a 85 .ANG. portion 212. Overlying the gate oxide 210 is the common floating gate 206. The 85 .ANG. portion 212 of the gate oxide 210 provides a tunneling oxide region to enable electrons to be applied to the floating gate 206 during erase and removed during programming. As with capacitor 106, capacitor 108 includes a programming junction region 214 to prevent depletion of the p type substrate during programming. The programming junction region 214 overlies both the 150 .ANG. portion 211 and the 85 .ANG. portion 212 of the tunneling oxide 210, even though the thin 85 .ANG. portion 212 is significantly degraded when grown over a programming junction region, creating leakage current.
As further shown in FIGS. 2A and 2C, transistor 110 is formed by a polysilicon (POLY) word line (WL) region 216 on the substrate with a portion of region 216 overlying n+ implant region 209 and another portion overlying an additional n+ implant region 218.
As shown in FIGS. 2A and 2D, transistor 104 includes two n+ implant regions 220 and 222 in the p substrate. A gate oxide region 224 of approximately 150 .ANG. is placed on the substrate bridging regions 222 and 220. The common floating gate 206 overlies the gate oxide region 224.
As shown in FIGS. 2A and 2E, transistor 102 includes two p type regions 230 and 232 included in a n+ type well 236 which is included in the p type substrate. A gate oxide region 238 of approximately 150 .ANG. is placed on the substrate bridging the regions 230 and 232. The common floating gate 206 overlies the gate oxide region 238.
The CMOS memory cell 100 is advantageous because it enables zero power operation, zero power operation indicating that a component does not continually draw power when the component is not changing states. For instance, with an appropriate voltage applied to the common floating gate 206, PMOS transistor 102 will conduct and NMOS transistor 104 will not conduct. Current will then be provided from Vcc through PMOS transistor 102 to the output until the output is charged up to Vcc. In this configuration, no current will be provided through NMOS transistor 104 to Vss. Further, with another voltage applied to the common floating gate 206, NMOS transistor 104 will conduct while PMOS transistor 102 does not. The output will then discharge to Vss. No additional current will be provided through PMOS transistor 102 from Vcc to Vss.
Although the CMOS memory cell design of FIG. 1 enables zero power operation as described, the CMOS cell 100 is not typically included in an array of memory cells on an integrated circuit chip. CMOS memory cells have previously not been considered practical because the threshold of the PMOS transistor 102 is referenced to Vcc. With Vcc being a voltage supplied from an external source to a chip Vcc pin, unregulated variations in Vcc occur. Such variations in Vcc require that an unacceptably high voltage be applied to the common floating gate to assure PMOS transistor 102 can be turned off.
Recently, it has been discovered that by applying a regulated voltage from a voltage reference to the source of PMOS transistor 102, rather than directly from Vcc, use of a CMOS memory cell 100 becomes practical. U.S. patent application Ser. No. 08/426,741 entitled "Reference for CMOS Memory Cell Having PMOS and NMOS Transistors With a Common Floating Gate" filed Apr. 21, 1995, (hereinafter, the CMOS reference patent application), incorporated herein by reference, discloses such a reference for a CMOS memory cell.